1. Technical Field
The present invention relates in general to semiconductor memory devices suitable for electrically erasable programmable read only memories (EEPROMs), and more particularly, is directed to MOS floating gate memory cells and memory arrays comprising dense contactless structures with direct write cell capabilities.
2. Description of the Prior Art
Non-volatile floating gate MOS memories are well known in the industry. In such devices, the conductive state of the transistor memory cell is determined by the voltage of the associated floating gate. Typically, a negatively charged floating gate is representative of a binary one state while an uncharged floating gate is representative of a binary zero state.
More particularly, a conventional electrically programmable read only memory (EPROM) utilizes a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over but insulated from a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate, but also insulated therefrom. The threshold voltage (V.sub.T) characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage (threshold) that must be applied to the control gate before the transistor is turned "on" to permit conduction between its source and drain regions is controlled by the level of charge on the floating gate. A transistor is programmed to one of two states by accelerating electrons from the substrate channel region, through a thin gate dielectric and onto the floating gate.
The memory cell transistor's state is read by placing an operating voltage across its source and drain and on its control gate, and then detecting the level of current flowing between the source and drain as to whether the device is programmed to be "on" or "off" at the control gate voltage selected. A specific, single cell in a two-dimensional array of EPROM cells is addressed for reading by application of a source-drain voltage to the source and drain lines in a column containing the cell being addressed, and application of a control gate voltage to the control gates in a row containing the cell being addressed.
One example of such a memory cell is a triple polysilicon, split channel electrically erasable and programmable read only memory (EEPROM). It is termed a "split channel" device since the floating and control gates extend over adjacent portions of the channel. This results in a transistor structure that operates as two transistors in series, one having a varying threshold in response to the charge level on the floating gate, and another that is unaffected by the floating gate charge but rather which operates in response to the voltage on the control gate as in any normal field effect transistor.
Such a memory cell is termed a "triple polysilicon" cell because it contains three conductive layers of polysilicon material. In addition to the floating and control gates, an erase gate is conventionally included. The erase gate passes through each memory cell transistor closely adjacent to a surface of the floating gate but insulated therefrom by a thin tunnel dielectric. Charge is then removed from the floating gate of the cell to the erase gate, when appropriate voltages are applied to all the transistor elements. An array of EEPROM cells are generally referred to as a "Flash" EEPROM array if an entire array of cells, or a significant group of cells, is erased simultaneously (i.e., in a flash).
Conventionally, to write data into a memory cell, the cell must be first erased and then written. Each of these operations takes approximately ten milliseconds, and each requires, for example, a 20 V supply of voltage. Decoder circuits are used to sustain the needed high voltages at the appropriate cells. These high voltage circuits generally do not scale down in size with the decreasing line widths now attainable with ever improving lithographic techniques. (By comparison, to read a device typically requires three to five volts applied and read cycle times are on the order of hundreds of nanoseconds.) Further, the required step of erasing the floating gate prior to writing data for storage thereon obviously adversely effects the operational speed of a semiconductor array of these type memories.